In general, to manufacture a semiconductor device, various unit processes including an exposure process, an ion implantation process, a chemical vapor deposition (CVD) process, an etching process, a cleaning process, etc., are repeatedly carried out on a semiconductor substrate to form a plurality of chips on the semiconductor substrate. Here, abnormal chips may be formed on the semiconductor substrate due to defects generated in the unit processes. Detections of the abnormal chips before sawing the semiconductor substrate, to form a plurality of semiconductor packages, may be advantageous in view of a yield and costs of manufacturing the semiconductor device.
Therefore, to determine whether the chips are normal or not, an electrical die sorting (EDS) process using a probing system is performed on the chips to test electrical characteristics of the chips. In the EDS process, probes make contact with contact pads on the chips. Test currents are applied to the contact pads through the probes. Electrical characteristics corresponding to outputted currents from the contact pads are compared to data in the probing system to determine whether the chips are normal or not.
A conventional cantilever type probe card includes a plurality of probe modules having a 4-by-8 chip arrangement in length and breadth, i.e., a (4×8=32) devices under test (32 DUTs), in accordance with a chip arrangement of an electronic device as an object.
A conventional method of manufacturing a probe card is illustrated with reference to FIGS. 1 to 5.
Referring to FIGS. 1 and 2, bumps 11 corresponding to pads on an object, such as an electronic device, are formed on a probe substrate 10.
Referring to FIGS. 3 and 4, a 6-inch probe module assembly 20, including probe tips 21 and supporting beams 22, is prepared. Here, the bumps 11, the probe tips 21 and the supporting beams 22 may be formed by a photolithography process and a plating process, etc.
Referring to FIG. 5, a solder paste P is coated on the bumps 11. The supporting beams 22 then make contact with the bumps 11, respectively. The bumps 11 and the supporting beams 22 are heated to a temperature of about 200° C. to about 350° C. to melt the solder paste P, thereby attaching the bumps 11 to the supporting beams 22, respectively. The probe module assembly 20 is then removed by an etching process to complete a conventional probe card.
Here, as semiconductor technologies have been rapidly developed, more chips are formed on a single semiconductor substrate to curtail costs of manufacturing a semiconductor device and to improve a yield of a semiconductor device. Thus, to test the chips, a probe card becomes larger. That is, as shown in FIGS. 6 and 7, a conventional probe card is manufactured using a 12-inch probe module assembly 40 to correspond the probe card to a probe substrate 30 that has an 8-by-16 chip arrangement, i.e., 128 DUTs.
When the DUTs of the probe substrate are increased from 32 to 128 or more, it is required to change the 6-inch probe module assembly into the 12-inch probe module assembly. Thus, compatibility of the conventional probe module assembly, in accordance with sizes of the probe substrates, may be reduced. That is, in the conventional method of manufacturing a probe card, the probe module assembly, having a large size that corresponds to that of the probe substrate, may be used.
Moreover, an apparatus for manufacturing a probe card is replaced with a new one suitable for manufacturing the probe module assembly having the large size. As a result, a time and costs for replacing the apparatus may be remarkably increased.
Further, it is required to use a large semiconductor substrate in proportion to the large size of the probe substrate. However, the large semiconductor substrate has poor flatness compared to that of a small semiconductor substrate so that a yield of the semiconductor device may be greatly reduced.
Furthermore, when at least one probe defect is generated on the semiconductor substrate, the probe defect is considered as a defect of a process for forming a probe card. Therefore, the probe defect with respect to the probes on the large semiconductor substrate may be higher than that with respect to the probes on the small semiconductor substrate.